▸ VLSI × AI × SILICON ENGINEERING

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THEHARDWARE
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KUSHAGRA BAKSHI // 2026

ABOUT

Where Silicon Meets Intelligence

I'm Kushagra — an Electronics Engineering student with hands-on roots in RTL design, UVM verification, and FPGA prototyping. My focus is the intersection of hardware and intelligence: making silicon smarter.

I'm currently building SiliconSpec — an AI-powered tool targeting the 70% of chip design time consumed by manual RTL verification. I'm the person who asks why verification still requires this much human effort, then builds the answer.

I'm looking for an internship where I can learn at the speed of silicon and contribute from day one.

HARDWARE
VerilogSystemVerilogUVMFormal VerificationFPGA
AI & SOFTWARE
PythonC/C++MATLAB/SimulinkTensorFlowPyTorch
EDA TOOLS
AMD VivadoModelSimQuartusGitLinux

THE ENGINE ROOM

What I Build

ACTIVE DEVELOPMENT

AI × RTL × VERIFICATION ENGINEERING

SiliconSpec — AI Auto-Verification Engine

alu_4bit.v
module alu_4bit (
  input  [3:0] a, b,
  input  [1:0] op,
  output reg [3:0] result
);
always @(*) begin
  case(op)
    2'b00: result = a + b;
    2'b01: result = a - b;
    2'b10: result = a & b;
    2'b11: result = a | b;
  endcase
end
endmodule
SiliconSpec AI v0.1
70% verification time targetAuto-generates SV testbenchesPre-simulation bug detection
COMING SOON
RTL Design Suite
4-bit ALU, UART controller, memory interfaces — SystemVerilog with full UVM testbench coverage.
IN BUILD
FPGA Prototyping Lab
Real-time logic deployment on Xilinx hardware with timing constraint analysis and synthesis reports.
RESEARCH
Neural Net → Silicon
Exploring HLS-based neural network acceleration — mapping ML inference to custom RTL datapaths for edge SoC deployment. Targeting sub-5ms inference on custom FPGA fabric.
VISION
The Problem I'm Building to Solve
70%
OF CHIP DESIGN TIME
Is consumed by verification — hunting functional bugs in RTL code before tape-out. One escaped bug costs millions. The process is largely manual, repetitive, and slow.
SiliconSpec is my answer. An AI-powered verification assistant that reads RTL code, understands design intent, and auto-generates SystemVerilog testbenches — flagging functional bugs before a single simulation runs.
Companies like Cadence and Synopsys are investing billions into AI for EDA. I'm building toward that problem from first principles as a 2nd year student.
Because the best time to solve hard problems is right now.
JOURNEY
The Timeline
2024
Started B.E. Electronics Engineering · VLSI Specialization
2024
First RTL designs — ALU, counters, UART in Verilog/SystemVerilog
2025
UVM Verification + FPGA Prototyping on Xilinx boards
2025
SiliconSpec concept born — AI meets RTL verification
NOW
Actively seeking internship at a world-class semiconductor company
CONTACT
Open to Internships.
Let's Talk.
[KUSHAGRA_EMAIL]
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KUSHAGRA BAKSHI × VLSI × AI × SILICON ENGINEERING × 2026